It’s not so simple:
https://stackoverflow.com/q/13102167
https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/
http://notabs.org/fpuaccuracy/index.htm
In short:
- IEEE 754 defines some instructions (like div), but not others (like sin)
- Intel has made serious bugs in its first div, sin, cos, etc implementations
- Intel Pentium’s fdiv bug was violating IEEE 754 spec so it was fixed
- fsin implementation wasn’t however mandated by IEEE 754 so Intel turned a bug into feature and maintains bug-compatibility with its first FPUs
- AMD maintains compatibility with Intel, but not 100%: I fed pseudo-random bits (converted to 80-bit long double using a C union) to /, sqrtl, sinl (implemented as x87 instructions), and hashed the results (converted back to bits), 1e6 times. The only difference I located was with sinl, which gave different hashes between Intel and AMD (but consistent between PIII and Core i7, as well as Athlon XP and Althlon 5050e). – fgrieu Oct 28 '12 at 20:36
- software compensates for hardware bugs to meet quality specifications, so maybe software also compensate for differences between CPU vendors?